1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to a semiconductor memory device having a voltage down converter for stabilizing internal power supply voltage level and for realizing higher speed of operation of internal circuitry such as a sense amplifier operating based on an internal power supply voltage.
2. Description of the Background Art
A voltage down converter (VDC) in a semiconductor memory device is disclosed, for example, in Japanese Patent Laying-Open Nos. 6-131869, 3-212893, 5-217370, in IEEE Journal of Solid-State Circuits vol. 24, No. 5, 1989, pp. 1170-1175, and in ISSCC Digest of Technical Papers, 1986, pp. 272-273.
FIG. 11 is a schematic diagram showing a semiconductor memory device having such a conventional voltage down converter (VDC).
Referring to FIG. 11, the VDC includes a level converting circuit 91 for converting level of an activating signal S generated in an internal circuitry 90, a one shot pulse generating circuit 93 for turning the output from level converting circuit 91 to a one shot pulse, and a P channel MOS transistor 15 (hereinafter referred to as a "PMOS") receiving at its gate the output from one shot generating circuit 93 and having its source connected to a node of external power supply voltage extVcc and its drain connected to a node of internal power supply voltage intVcc.
Further, the VDC includes a reference voltage generating circuit 97, a current mirror amplifier 11 for comparing a reference voltage V.sub.REF generated by the reference voltage generating circuit 97 with the voltage level of internal power supply voltage intVcc and a PMOS 13 receiving at its gate the output from current mirror amplifier 11 and having its source connected to the node of external power supply voltage extVcc and its drain connected to the node of internal power supply voltage intVcc.
FIG. 12 is a diagram of signal waveforms in the semiconductor memory device having the VDC shown in FIG. 11.
The operation of the semiconductor memory device having the VDC of FIG. 11 will be described with reference to FIG. 12.
It is assumed that at time t.sub.1, internal circuitry 90 consumes much current from the voltage level of internal power supply voltage intVcc and the level at the node of the internal power supply voltage intVcc begins to lower.
At time t.sub.0 before the start of lowering of the level of internal power supply voltage intVcc, activating signal S changes from "L" (Low) to "H" (High) (intVcc level), and in response, the voltage level at node N1 changes from "L" to "H" (extVcc level) by the operation of level converting circuit 91.
By the one shot pulse generating circuit 93, there is a one shot pulse on the side of "L" is generated at node N2 between times t.sub.1 and t.sub.3.
During this period, PMOS 15 is on, and voltage is rapidly supplied from the node of external power supply voltage Vcc to the node of internal power supply voltage intVcc.
Further, at time t.sub.2, because of the function of current mirror amplifier 11 incidental to the level lowering of internal power supply intVcc, the voltage level at node N3 lowers gradually, and hence PMOS 13 turns on, so that voltage is applied from the node of external power supply voltage extVcc to the node of internal power supply voltage intVcc.
At time t4, when the voltage level of internal power supply voltage intVcc is recovered, the voltage level at node N3 is also recovered, and PMOS 13 turns off.
In this manner, in the semiconductor memory device having a conventional VDC, voltage is supplied from the node of external power supply voltage extVcc to the node of internal power supply voltage intVcc by a one shot pulse in response to a prescribed signal generated from an internal circuit, timed with lowering of the voltage level of internal power supply voltage intVcc.
Further, current mirror amplifier 11 detects actual lowering of the voltage level in internal power supply voltage intVcc and turns PMOS 13 on, so that voltage is supplied from the node of external power supply voltage extVcc to the node of internal power supply voltage intVcc.
However, even when the structure of FIG. 11 is used, the voltage level of internal power supply voltage intVcc still lowers by .DELTA.V. Further, it takes time (t.sub.4 -t.sub.1) until the voltage level of internal power supply voltage intVcc is fully recovered.
Accordingly, operations of the internal circuitry 90 and peripheral circuits, not shown, may be affected.